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This work proposes and analyzes an intuitive time-distributed procedure for estimating the effective number of bits (ENOB) of ADCs during the design phase. Two derived numbers, the ENOB lower-bound and the ENOB upper-bound, signal to a designer whether the design has satisfied the desired quality, or either further circuit improvement or a more accurate time-distributed procedure is necessary. The result enables designers to employ the procedure to almost linearly reduce the ENOB simulation waiting time with a controllable loss of accuracy. Two successive approximation register (SAR) ADC designs demonstrate the effectiveness of the procedure, one of which has been manufactured

Time-distributed procedure for fast estimation of effective number of bits during ADC Design