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In order to fabricate metal gate/high-k gate stacks utilizing ECR sputtering, selective etching of HfN gate electrodes was investigated. It was found that etching rates of HfN gate electrodes at room temperature were 2.9 and 0.23nm/s for DHF (1%) and the mixed solution of HF:H2O2:H2O = 1:2:40, respectively. In addition, the etching selectivity for HfN/HfSiON was relatively high, such as the ratio of 65 which was 3 times higher than that of DHF (1%) by the mixed solution. After the in-situ formation of HfN/HfSiON layers on p-Si(100) and post deposition annealing (PDA), pattering of HfN was carried out utilizing the selective etching process. In case the PDA of 800°C/15s, the MOS diodes were found to be successfully fabricated, and the equivalent oxide thickness (EOT) of 0.56nm, and the leakage current at VFB-1 V of 1.3A/cm2 were obtained.

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations