English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10 ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100μW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG.

Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs