English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

This work presents a frequency multiplier architecture using 50% duty cycle corrector of which it can double input clock frequency in a wide-range operation. The said frequency multiplier is simulated using a 0.18µm CMOS process parameters and the results show that the output operational frequency attained a wide range from 10-MHz to 2-GHz. Moreover, the proposed design dissipates a power consumption of 1.4mW and a lock time of 1.2us at 2-GHz output signal.

Frequency multiplier using 50% duty cycle corrector