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This paper describes theoretical approach and proposed scheme of wide data bus architecture using charge-recycling and stacked I/O for signal transmission via TSV (Through Silicon Via). This data bus is assumed for vertical stacked chips of 3D integration. This theoretical approach is based on probability calculation for data stream on pure random pattern. Through the calculation, power reduction ratio to normal data bus (non-charge recycling) is clarified in given conditions for power estimation in early design stage. The proposed scheme for data and clock transmission adopts Local Voltage Stabilizer (LVS) and compact level shifter for capacitor area and clock power reduction. Simulation results show that the proposed 2 story data bus architectures of 64bits (32×2) and 128bits (64×2) achieve competitive power efficiency (0.160 pJ/bit) with smaller size (44% to prior work) and normal operation voltage (1 V). These achievements are in dense TSVs (40μm pitch), standard 65 nm process technology and PRBS9 data stream. key words: Signal Transmission, Charge Recycling, Stacked I/O Classification: Electron devices, circuits and modules

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus