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A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a single-ended successive approximation register (SAR) analog-to-digital converter (ADC). The 10bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8V. Its active area and power consumption are 0.207mm2 and 2.29mW, respectively. The measured DNL and INL are +0.93/−0.51 LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range