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A mm-wave 5-bit digital attenuator with low RMS (root mean square) amplitude error and low phase variation is presented in 65 nm CMOS. The attenuator combines the PI/T-type topology with embedded switches and PI-type topology with the SPDT (single-pole-double-throw) switches to alleviate the insertion loss issue of the conventional PI/Ttype topology with embedded switches in mm-wave frequency band, and achieves high attenuation range while maintaining compact chip size. The amplitude/phase calibration technique is proposed to reduce the RMS amplitude error/phase variation and improve the circuit robustness. The presented attenuator has been integrated in a Ka-band phased-array transmit front-end module and achieves 15.5 dB attenuation coverage with the step of 0.5 dB. The RMS amplitude error and RMS phase variation are 0.130.48 dB and 1.24-2.08◦ across 25-35 GHz, respectively. Especially, the proposed attenuator could achieve the RMS amplitude error of 0.13-0.25 dB if the operation frequency is limited to 26.9-31.4 GHz. The core chip size is 434 μm × 360 μm. key words: PI/T-type topology, attenuator, CMOS, Ka-band, phased-array Classification: Integrated circuits (memory, logic, analog, RF, sensor)

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS