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An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper. The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA. The low-voltage DCO uses current-reuse structure to achieve lower and use bridging-capacitance technique to achieve high frequency resolution. The proposed design is validated by the ADPLL fabricated in the 65-nm CMOS technology. The measurement results show that the in-band and out-band phase noises are −90 dBc/Hz@10kHz offset and −130 dBc/Hz@1MHz offset, respectively. The RMS and peak-peak jitter are 1.24 ps and 8.65 ps respectively.

An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO