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A 33Gbit/s equalizer chip fabricated in 0.13 μm BiCMOS technology is presented. The proposed equalizer prototype includes adaptive continue time linear equalizer (CTLE) with middle frequency compensation and adaptive half-rate look ahead decision feedback equalizer (DFE). The slope detection based CTLE employs a two-path amplifier to adjust the ratio of the high frequency and low frequency adaptively, and a middle frequency amplifier dedicated to provide an appropriate compensation in the intermediate frequency range. For the half-rate DFE, by using a look ahead structure and an analog LMS algorithm circuit, the performance is improved in speed and area. Measurement results show that the equalizer chip can compensate lossy channel with a loss of 26 dB at 20GHz effectively and the data rate can be up to 33Gb/s under 3.3V power supply, the total power consumption is about 726mW at 33Gb/s data rate.

A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link