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This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01mm2. Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25GHz and the loop bandwidth can be kept around 20MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300MHz is 780 fs at carrier frequency of 6.25GHz and maximum power efficiency is 0.496mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.

A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter