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As the main component for modern main memory system, DRAM stores data by capacitors, which must be refreshed periodically to keep the charges. As the size and speed of DRAM devices continue to increase, the overhead of refresh has caused a great power and performance dissipation. In this paper, we proposed a CAM (content-addressable memory)-based Retention-Aware DRAM (CRA-DRAM) system, a hardware implementation that uses CAM and RAM to locate and replace the leaky cells at the IO granularity. Then the entire DRAM is refreshed at a much lower rate. With IO-granularity address of leaky cells stored in CAM at the profiling stage, each access address to CRA-DRAM would be searched to determine where the data are read from or written to. We proved the IOgranularity data replacement technique is completely compatible with the JEDEC standard. The experimental results show that when the refresh period is increased by 6×, CRA-DRAM has a 82.5% refresh reduction, an average DRAM energy reduction of 29.1% and an average system performance improvement of 8.3%. Without modification to memory controller, OS and DRAM devices, CRA-DRAM is quite promising to be applied in DIMM, HBM and HMC.

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction