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A reference column is employed to improve the read performance of phase change memory (PCM). In this way, a changeable reference current replaces the constant one; both the reference cell and the selected cell have the same bit line (BL) parasitic parameters and read transmission gate parasitic parameters in the read operation. Simulated in a 40 nm CMOS process, read access time of 4-Mb PCM is 30.65 ns with 190.9 ns improvement. Monte Carlo simulations show a 80.5 ns worst read access time compared to the conventional 1.58 μs.

Enhanced read performance for phase change memory using a reference column