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A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noisetolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02mm2. The DLL operates over a frequency range of 0.3–2.0GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48mW from a 1.1V supply at 1GHz.

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs