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This letter reports an extremely small differential non-linearity (DNL) in a cyclic analog-to-digital converter (ADC) using depletion-mode MOS (DMOS) capacitors for CMOS image sensors (CISs). Compared with conventional 1.5b digital-to-analog converter (DAC) configuration using 3 reference signals, the cyclic ADC with split sampling DMOS capacitors in the 1.5b DAC has the maximum DNL of +0.125/-0.125 LSB at 14b despite the large applied voltage dependency of the DMOS capacitors of 2.47%.

Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors