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A novel technique is proposed to mitigate the SERs of combinational circuits by using the half guard band. During the layout placement, by sharing the guard band between physically adjacent cells, the soft error rates (SERs) can be effectively reduced with less performance penalty. Threedimensional technology computer-aided design (TCAD) numerical simulation and circuit-level simulation are adopted to demonstrate the hardening performance.

Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology