English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

An all-digital on-chip delay measurement (OCDM) architecture with high delay measurement resolution and low supply voltage sensitivity for efficiently detection and diagnosis in the high performance system-on-chip (SoC) applications is presented. Based on the proposed differential delay line pair (DDLP) and an cascadestage delay line, the quantization resolution of the proposed OCDM not only has a high immunity to supply voltage variations without an extra self-biasing or calibration circuit, but also achieves to several picoseconds. Simulation results show that delay measurement resolution can be improved to 1.04 ps, and the average delay resolution variation is 11 fs with ±10% supply voltage variations. In addition, the proposed design can be implemented in all-digital design manner, making it very suitable for SoC applications as well as system-level integration.

High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications