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A 1.0 GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42 fJ/Conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new fulldigital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the area of chip grandly. A new linear and continues offset voltages of dynamic comparator calibration method is presented. This ADC implemented in 65 nm CMOS technology achieves SNDR of 48.5 dB and SFDR of 58.7 dB for 479.5 MHz input frequency at the rate of 1.0-GS/s. And the SNDR and SFDR maintain above 48 dB and 55 dB, respectively, up to 995.1 MHz. The power consumption is only 17 mW with a supply voltage of 1.2 V.

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth