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In this paper, we propose a comprehensive scheme that simultaneously achieves IP protection in both after-sale and evaluation periods. Our key idea is to build a pre-verification path into an active metering structure, with a non-functional defect purposely attached to the path, rendering any potential pirating users unwilling to risk the defective behavior of the fabricated chips. Using the MCNC’91 benchmarks, we achieve a large area-to-power ratio proving the feasibility of our scheme. At the same time, compared with a well-known metering scheme, the proposed scheme can significantly improve the robustness against brute-force attack, roughly by an average value of 2 per layer. The scheme can also reduce the area and power overhead by 4.4% and 11.2% on average considering an extra 5 to 10 layers.

A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design