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A new frequency offset compensation technique for the MIPI Low Latency Interface (LLI) application is proposed. The proposed clock and data recovery (CDR) circuit has a composite structure of bang-bang and oversampling phase detectors with an offset estimator. Digitally estimated frequency offset is used to determine the gain of the 2nd order digital CDR. An elastic FIFO for the oversampled multi-phase data stream is not needed, because the proposed offset estimator can compensate for frequency offset instead. With a frequency offset ranging from 60,000 ppm to +60,000 ppm, the proposed CDR has a very fast and almost constant lock acquisition time of less than 15 unit intervals and a short recovery logic latency of 1 unit interval. The proposed digital CDR is implemented using 65-nm CMOS technology. It consumes 5.1mW from a 1.2-V power supply at 5.8Gb/s.

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications