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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. Most of the synthesis tools developed for them are based on the "unate paradigm". Therefore, their output is optimal only for AND-OR architectures. However, many common functions are (nearly) linear like counters, adders, multipliers, and parity generators. The design of those functions with such synthesis tools is very inefficient. Therefore, synthesis tools which allow the synthesis with EXOR gates have been demanded. Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel $ACT\sp{TM}$ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates. To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces synthesis methods based on an extended theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The presented synthesis concepts take advantage of the global information obtained by the introduced spectral methods. Based on these synthesis concepts circuit realizations for FPGAs with fewer macrocells are obtained. Specifically, for (nearly) linear functions a reduction of up to 50% is found. Moreover, while circuits obtained by other FPGA technology mappers are difficult to place and route, the circuits obtained by the presented synthesis concepts are easily routable. This is due to the obtained level-by-level circuit realizations where connections exist only between two levels. Therefore, the developed synthesis methods are especially suitable for fine grain FPGAs like from Concurrent Logic which have very limited routing resources.

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping