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In recent years power saving is one of the important thing. Domino logic circuit is power efficient cicuit,so it is widely used in variety of applications in digital design. But it has a limitation of low noise immunity and more leakage current. This problem can be solved by using keeper transistor to compensate leakage current of pull down network. The conventional keeper domino circuit reduces the performance and more power consumption due to the contention between keeper transistor and pull down network. This problem is more in wide fan in gates due to large number of leaky paths connected to the dynamic node. In this paper ,a new technique is proposed which overcomes the contention problem and reduces power dissipation and provide high noise immunity. Simulations of wide fan in gates are designed using TSMC 180nm technology with Vdd=1V at 27°c and 110°c using mentor graphics.

Power Efficient and Noise Immune Domino Logic for Wide Fan in Gates