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LDO voltage regulators compose a small subset of the power supply arena. Low-drop-out (LDO) voltage regulators are used in analog applications that generally require low noise and high accuracy power rails. Voltage regulators provide a constant voltage supply rail under certain loading conditions. Circuits that are not performing tasks are temporarily turned off lowering the overall power consumption. The LDO voltage regulator, therefore, must respond quickly to system demands and power up connected circuits. To motivate new aspect of power management towards a design of a low drop-out voltage regulator that fulfils the present industry requirements as well as the upcoming demands of the future, it becomes necessary to design the LDO regulator which gives overall performance. A low-voltage low-dropout regulator that uses an Vdd of 1 V to an output of 0.8–0.74 V, with 32-nm CMOS technology is proposed. By scaling down the technology, we can get lower power consumption. More emphasis is given on the compactness and low drop-out voltage. The latest power management unit concept inside the system on chip (Soc) scheme inspires the digital control potential for the design of a novel LDO regulator. A simple operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique which is able to boost the gain. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is adopted. Programmability is added by applying two external control signals. These advantages allow the proposed LDO regulator to achieve a 60-mV output variation for low load transient, area efficient architecture with low power consumption.

VLSI IMPLEMENTATION OF A PROGRAMMABLE LOW DROP-OUT VOLTAGE REGULATOR