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The fundamental unit of building a Network on Chip is the router , it directs the packets according to a routing algorithm to the desired host. In this paper ,a router is designed using VERILOG language and implemented on Spartan 3E FPGA with the help of Integrated software environment ( ISE10.1) . The utilization of the Spartan 3E resources is excellent ( for example the number of slices required doesn’t exceed 3%) .After that a (2×2) mesh topology and a (2x2) torus topology network is designed and implemented using FPGA . An example is applied on the designed Network on Chip (NoC) which validates the design successfully.

FPGA BASED: DESIGN AND IMPLEMENTATION OF NOC TORUS TOPOLOGY