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Digital signal processing, Digital control systems, Telecommunication, Audio and Video processing are important applications in VLSI. Design and implementation of DSP systems wit h advances in VLSI demands low power, efficiency in energy, portability, reliability and miniaturization. In digital signal processing, linear-time invariant systems are impo rtant sub-class of systems and are the heart and soul of DSP. In many application areas, linear and circular conv olution are fundamental computations. Convolution with very long sequences is often required. Discrete linear convolution of two finite-length and infinite length sequences using c ircular convolution on for Overlap-Add and Overlap-Save methods can be compute d. In real-time signal processing, circular convol ution is much more effective than linear convolution. Circular convolu tion is simpler to compute and produces less output samples compared to linear convolution. Also linear convolution can be comput ed from circular convolution. In this paper, both linear, circular convolutions are performed using vedic multiplier architecture based on vertical and cross wise algorithm of Urdhva-Tir yabhyam. The implementation uses hierarchical design approach which leads to im provement in computational speed, power reduction, minimization in hardware resources and area. Coding is done using Verilog H DL. Simulation and synthesis are performed using X ilinx FPGA.

A NOVEL APPROACH FOR HIGH SPEED CONVOLUTION OF FINITE AND INFINITE LENGTH SEQUENCES USING VEDIC MATHEMATICS