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The effectiveness of data processing in the reconfigurable computer systems depends significantly on the unproductive time costs of the reconfiguration of the FPGA computational space. It is an important modern problem that hinders the intensive progress of reconfigurable computations. The aim of the research is to improve the efficiency of the process of tasks mapping into the reconfigurable computing structure of the dynamically RCs by reducing the communication delays when the reconfiguring FPGA space in the Run Time mode. Mathematical models for determining the main efficiency criteria of the dynamically RCs and estimating the execution time of the main stages of adaptive tasks mapping that take into consideration the influence of delays of the configuration data transfer at all organization levels of the system are proposed. The concept of adaptive tasks mapping into the dynamically reconfigurable FPGA space based on the new approach to the transformation of algorithms’ MDG and the multilevel configuration data caching is proposed and formalized. That allows the realization of various strategies of adaptive tasks mapping based on the criteria of overhead time minimization considering FPGA hardware limitations and parameters of the changing computing environment during the tasks mapping. The experiments showed that the use of adaptive tasks mapping allows to reduce the overhead time and increase the effectiveness of reconfigurable computations for executing the algorithms with frequent repetition of similar tasks.

Formalization of the concept of adaptive tasks mapping in the reconfigurable computers on FPGA