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International audienceA novel vertical nanoporous structure is reported as a starting point for the fabrication of a fully-surround gate field effect transistor (FET) based on well-ordered nanostructures array. The proposed porous stacking is perfectly suited both for the collective organization of high density (up to 1011.cm-2) arrays of nanostructures like nanowires (NWs) or nanotubes (NTs), as with calibrated diameters (during growth), as well as for easing the Source, Gate, and Drain electrodes connections for individual or groups of nanostructures. Moreover the unique fully-surround gate architecture enables a quasi-ideal coupling between the gate and the channel, theoretically leading to improved devices performance and reduced global power consumption. In this paper we describe the main steps for this versatile and lithography-free technique to fabricate a multi-layer porous template down to the nanometer scale, as well as the first nanostructures (carbon NTs) growth attempts inside such functional template. We highlight the fact that the proposed porous structure may acts as a passive template for the one-dimensional nanomaterials growth as well as an active element in the future device. The proposed approach is in line with bottom-up fabrication approach to provide smaller devices, and is fully-compatible with classical processes used in the silicon industry

A new vertical nanoporous functional structure process fabrication to control one dimensional nanostructure growth