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An approach to specification, verification and construction of PLC programs for discrete problems is proposed. For the specification of the program behavior, we use the linear-time temporal logic LTL. Programming is carried out in ST, IL and LD languages according to an LTL-specification. The correctness analysis of an LTL-specification is carried out by the symbolic model checking tool Cadence SMV. A new approach to PLCprogramming is shown by an example. For a discrete problem, we give an ST-program, its LTL-specification and an SMV-model.

LTL-Specification, Verification and Construction of PLC Programs