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The current article addresses digital implementation of new demodulation schemes for Binary Frequency Shift Keying (BFSK), and has two main objectives: of the description of the performance of the new processing method and its implementation on FPGA technology. Performance is analyzed by means of the total number of demodulated bits free of errors without noise, and by means of the BER parameter. The proposed method exhibits to have better performance than the solutions reported. Additionally, the solution obtained shows lower complexity than reported methods in regard to the total number of adders and multipliers. The implementation is described for FPGA systems, and the System Generator software is used for testing and simulating the results.

New digital demodulator with matched filters and curve segmentation techniques for BFSK demodulation: FPGA implementation and results