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With the rise of the number of electronic portable devices, the importance of leakage power reduction techniques are increasing. Leakage power dissipation has become one of the critical issues in modern integrated circuit. This work focuses on the low power circuit design, which is showing an ever increasing growth with the scaling of technology nodes. Supply voltage and threshold voltage of the device are scaled down to maintain the performance at lower technology nodes. Reduction in threshold voltage causes leakage power in the concerned device. The number of gates per chip has been increasing with technology scaling which resulted in large leakage power dissipation. The demand of low power integrated circuits is increasing to improve the performance of portable systems. In this research paper, a low leakage circuit level approach is proposed in order to overcome the leakage power dissipation. 4:1 multiplexer is designed and simulated at 32nm technology node by using proposed approach and the results are compared with the conventional 4:1 multiplexer circuit. Keywords—Device scaling, leakage power, nanoscale CMOS, VLSI circuits.

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits