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SystemC has become the de facto standard for modeling and simulation in hwsw co-design. However, existing verification techniques for SystemC are mostly ad hoc and non-systematic. To overcome this problem, we present a systematic, comprehensive, and formally founded framework for hwsw co-verification of SystemC designs. The framework is based on a formal definition of the semantics of SystemC and uses a combination of model checking and conformance testing. With that, it facilitates automated verification and validation throughout the whole design process. We demonstrate the performance of our approach with two case studies, namely a packet switch and an anti-slip regulation and anti-lock braking system.}.

Automated HW/SW Co-Verification of SystemC Designs Using Timed Automata