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The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects — NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level