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How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “ p-n-p ”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “ p-n-p-n-p ”-arranged-type SCR in the drain side (diffusion regions of the drain side is  P  + - N  + - P  + - N  + - P  + ). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to I t2  robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the I t2  robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P +  discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their I t2  values have reached above 6 A; however, the major repercussion is that the V h  value will be decreased about 66.7 ~ 73.7%.

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices