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This chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.

A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications