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An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor’s transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of –28 dBm for a bit error rate of 10 –10  at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm 2  and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range