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The article presents performance tests of code executed by STM32 microcontrollers using a virtual machine (so-called intermediate code) dedicated to control systems. The ARM architecture used in these chips has limitations related to access to non-aligned addresses. Three ways to overcome these limitations have been proposed, and each has been subjected to a suite of tests to determine their performance. Tests were conducted for two operating modes, i.e. with 16- and 32-bit addressing for different generations of chips. The test results allow to choose the right solution for a specific platform.

The Performance of Executing Intermediate Code for Control Systems Using STM32 Architecture