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The SRAM (static random access memory) extensively used in computers, embedding hardware, and other digital systems is a main source of power dissipations. In order to reduce the increasing power dissipation of the SRAM, a low-power adiabatic SRAM is introduced. The proposed SRAM is realized by PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) to reduce its dynamic energy consumption. The GLB (gate-length biasing) and DTCMOS (dual-threshold CMOS) techniques are used to reduce its leakage consumption. An improved storage cell is used to reduce the power dissipation of the storage array. The proposed SRAM based on PAL-2N with GLB and DTCMOS techniques is investigated with different source voltages in terms of energy dissipation and maximum operating frequency. All circuits are simulated with HSPICE using SMIC 130nm CMOS technology. The results show that the proposed SRAM attain 80% energy saves compared with the static SARM at 1.2V source voltage. In addition, the simulation results also show that the super-threshold adiabatic SRAM operating in medium strong inversion regions achieves low energy dissipation with reasonable operating speed.

Super-Threshold Adiabatic SRAM Based On PAL-2N Operating In Medium Strong Inversion Region