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The generation of computer-generated holograms (CGHs) requires a significant amount of computational power. To accelerate the process, highly parallel field-programmable gate arrays (FPGAs) are deemed to be a promising computing platform to implement non-iterative hologram generation algorithms. In this paper, we present a cost-optimized heterogeneous FPGA architecture based on a one-step phase retrieval algorithm for CGH generation. The results indicate that our hardware implementation is 2.5× faster than the equivalent software implementation on a personal computer with a high-end multi-core CPU. Trade-offs between cost and performance are demonstrated, and we show that the proposed heterogeneous architecture can be used in a compact display system that is cost and size optimized.

Cost-optimized heterogeneous FPGA architecture for non-iterative hologram generation