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With the development of integrated circuit technology, system-on-chip (SoC)integration has become the mainstream method of VLSI design. SoC design usually has three features: emphasis on top-down design, outstanding design reusability, and need of low-power facilities, which brings great challenges to design for testability (DFT). This paper proposes a complete DFT scheme for a heterogeneous multi-core system-on-chip on multimedia processing, DPU-m. The proposed DFT scheme supports three operation modes: function mode, memory built-in self-test mode (BIST)and scan test mode. This thesis uses a top-down and modular design method for the DFT of DPU-m logic circuit. It proposes and implements a distributed and multiplexed test access mechanism; Experimental results show that test coverage of the single stuck-at fault for DPU-m logic circuit is 98.58%, which meets the requirements of the designer. In order to meet the need of at-speed testing, this thesis designs and implements an on-chip clock controller based on an on-chip clock generator, which supports at-speed testing of different clock domains. This thesis designs and implements a serial and parallel combined BIST structure for the on-chip memory, which meets the constraints of test power and reduces test time. Then, this thesis designs and implements the test results output circuit, with a memory diagnostic resolution meeting the requirements of the designer; the results show that the test time for memories is 14 ms at the test frequency of 100 MHz.

一款用于多媒体处理的异构多核系统芯片的可测试性设计