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This paper presents a practical method of po- tential replacement of several different Quasi-Cyclic Low- Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to imple- ment the LDPC encoder and decoder in a memory-con- strained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algo- rithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the pro- posed LDPC setup simplification. Finally, the error per- formance of the modified system structure is evaluated and compared with the original system structure by means of simulation.

Analysis of Minimal LDPC Decoder System on a Chip Implementation