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Public key cryptography protocols, such as RSA and elliptic curvecryptography, will be rendered insecure by Shor's algorithm when large-scalequantum computers are built. Cryptographers are working on quantum-resistantalgorithms, and lattice-based cryptography has emerged as a prime candidate.However, high computational complexity of these algorithms makes it challengingto implement lattice-based protocols on low-power embedded devices. To addressthis challenge, we present Sapphire - a lattice cryptography processor withconfigurable parameters. Efficient sampling, with a SHA-3-based PRNG, providestwo orders of magnitude energy savings; a single-port RAM-based numbertheoretic transform memory architecture is proposed, which provides 124k-gatearea savings; while a low-power modular arithmetic unit accelerates polynomialcomputations. Our test chip was fabricated in TSMC 40nm low-power CMOS process,with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106klogic gates and 40.25 KB SRAM. Sapphire can be programmed with custominstructions for polynomial arithmetic and sampling, and it is coupled with alow-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-basedCCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA,CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitudeimprovement in performance and energy-efficiency compared to state-of-the-arthardware implementations. All key building blocks of Sapphire are constant-timeand secure against timing and simple power analysis side-channel attacks. Wealso discuss how masking-based DPA countermeasures can be implemented on theSapphire core without any changes to the hardware.

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols