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Ultra Deep-Sub-Micron CMOS chips have to function correctly and reliably, notonly during their early post-fabrication life, but also for their entire lifespan. In this paper, we present an architectural-level in-field repairtechnique. The key idea is to trade area for reliability by adding repairfeatures to the system while keeping the power and the performance overheads aslow as possible. In the case of permanent faults, spare blocks will replace thefaulty blocks on the fly. Meanwhile by shutting down the main logic blocks,partial threshold voltage recovery can be achieved which will alleviate theageing-related delays and timing issues. The technique can avoid fatalshut-downs in the system and will decrease the down-time, hence theavailability of such a system will be preserved. We have implemented theproposed idea on a pipelined processor core using a conventional ASIC designflow. The simulation results show that by tolerating about 70% area overheadand less than 18% power overhead we can dramatically increase the reliabilityand decrease the downtime of the processor.

In-Field Logic Repair of Deep Sub-Micron CMOS Processors