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The motivation of this work is to understand the effects of tool properties and downfeed (or infeed) method on the planarization of a patterned Si wafer. In oxide or interlevel dielectric (ILD) planarization process, the major concerns are the global planarity, oxide thickness differences in different regions across the chip and the remaining local step height (or height differences in oxide over the patterned features and between pattered features). By extending the MIT density-and-step height dependent model, this paper aims to establishing an analytical model to incorporate the tool stiffness and infeed scheme. A 2D simulation has also been performed to show the model validity and the effects of tool stiffness and infeed scheme on the planarity of wafer.

Simulation on Planarization Process of Patterned Si Wafer(Establishment of an Analytical Model)