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This is the summary of first three years of activity of the EURETILE FP7project 247846. EURETILE investigates and implements brain-inspired andfault-tolerant foundational innovations to the system architecture of massivelyparallel tiled computer architectures and the corresponding programmingparadigm. The execution targets are a many-tile HW platform, and a many-tilesimulator. A set of SW process - HW tile mapping candidates is generated by theholistic SW tool-chain using a combination of analytic and bio-inspiredmethods. The Hardware dependent Software is then generated, providing OSservices with maximum efficiency/minimal overhead. The many-tile simulatorcollects profiling data, closing the loop of the SW tool chain. Fine-grainparallelism inside processes is exploited by optimized intra-tile compilationtechniques, but the project focus is above the level of the elementary tile.The elementary HW tile is a multi-processor, which includes a fault tolerantDistributed Network Processor (for inter-tile communication) and ASIPaccelerators. Furthermore, EURETILE investigates and implements the innovationsfor equipping the elementary HW tile with high-bandwidth, low-latencybrain-like inter-tile communication emulating 3 levels of connection hierarchy,namely neural columns, cortical areas and cortex, and develops a dedicatedcortical simulation benchmark: DPSNN-STDP (Distributed Polychronous SpikingNeural Net with synaptic Spiking Time Dependent Plasticity). EURETILE leverageson the multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPESIntegrated Project (2006-2009).

EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment