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Generally, the load capacity of the integrated gate circuit depends on its output low-level property. This paper gives a theoretical and experimental study on the output low-level volt-ampere property of the current popular TTL NAND-gate SN74LS00N, and the true output property model and reasonable parameters that are considered to be inconsistent with those in relevant classical textbooks. In addition, with the actual measurement of the change of the power supply current of each gate under different logic states, the method and specific values of the key circuit parameters of the internal part of the integrated circuit—the input stage resistor R1 and the inverting stage pull-up resistor R2—are given. This will play an active role in understanding the TTL 74LS series of electronic device circuits and their experimental teaching, related electronic engineering design, as well as the writing, publishing and teaching of the textbooks. Introduction The explanation of the TTL gate circuit is the popular and necessary content of the teaching of "Digital Electronic Technology" in Chinese universities [1-2], but most of the textbooks only explain the so-called "standard 74 TTL series" gate circuit that has long been outdated, although some also mention that the 74LS series of gates have been in use for more than 50 years but are still widely used. Therefore, it is rare to focus on the 74LS series of gates in the textbooks, and naturally it is inevitable that there is no detail description on 74LS gates [3-12]. This paper measures the output low-level volt-ampere property curve VOL-IOL of the TTL "four NAND gate" SN74LS00N gate circuit (manufactured by HLF, Huilyf, China) with high level inputs when the output is unloaded, which is supplemented by the measured power supply current ICC of each gate under different logic states. This report gives the theoretical explanation of the volt-ampere property curve VOL-IOL, and strives to enrich all the contents of the "Digital Electronic Technology" textbooks explaining the 74LS00 gate circuit. The Principle Circuit of the 74LS00 NAND Gate The principle circuit of 74LS00 NAND gate is shown in Figure 1 [6]. The figure shows the theoretical design values of the involved various resistors R1, 2, 4, 5, 6, and RB, C. This article does not cover its full voltage transfer property VO-VI, input volt-ampere property VI-II (this property at the input low-level state with no negative voltage is equivalent to the input load property), output high-level property VOH-IOH, fan-out performance, noise tolerance, etc. Here, only the circuit parameters (the resistor R1 at the input stage and the pull-up resistor R2 at the inverting stage) and the overall low-level-output property of the internal part of the integrated circuit are discussed, so the values of R1, 2 are the most important in this paper, and assuming that the turn-on voltage VD of the Schottky diode D1, 2 is constant at 0.3 V, the emitter junction of the anti-saturation Schottky transistor T2, 5 is sufficiently conductive with a bias voltage of VBE = 0.7 V.

Study on the Output Low-Level Property of the SN74LS00N Chip