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Dynamic Reconfigurable Systems (DRSs) have been accepted as an important alternative for lowering costs of digital circuits. However, they add new dimensions to the system-on-chip (SoC) design space. Although new methodologies have been proposed by Field Programmable Gate Arrays (FPGAs) manufacturers to deal with the increased design complexity in this class of circuits, solutions to the algorithmic and block level design are still very ad-hoc. Considering the generalized use of robust communication resources in current complex SoCs, structured communication means, as network-on-chips (NoCs), have been included in dynamic reconfigurable systems generating DRSs based on NoCs, or DRS-NoCs, under different architectures. DRS-NoC architectures can be simple or complex. Simple DRS-NoCs architectures refer to regular and direct NoC topologies, with homogeneous Processing Modules (PMs). Complex DRS-NoCs architectures refer to irregular and undirected NoC topologies, with heterogeneous MPs. Mapping is the step in the SoC design flow which aims to find the best topological location for the application processing units onto the NoC topology, such that the metrics of interest can be greatly optimized. The placement problem deals with the optimized allocation of resources (cores) inside the reconfigurable device. In DRS-NoCs mapping, the on-going reconfiguration capability adds a new dimension to the mapping problem, since different cores are assigned to the same router, but being present in the in the logic fabric in separate moments. Furthermore, in complex DRS-NoC architectures the mapping problem is strongly associated with the placement one, and they should be dealt concurrently. To the date, the mapping and placement problems have not been properly addressed for those kind of architectures. In this work solutions are presented for hardware core placement and/or mapping for both simple and complex DRS-NoC architectures. Firstly, a mapping strategy is proposed for simple architectures, in a way that makes it possible to use previous classic mapping strategies (without reconfiguration) for DRSs. Results show reductions up to 38% on the average NoC delay and up to 41% of energy saving when comparing the best solution with average random solutions. In the second phase, the mapping and placement problems are dealt concurrently for DRS-NoC complex architectures: the problem formalization is proposed and for its analysis, an exact, and semi-exaustive, algorithm is implemented and applied. Due to the high complexity associated to the problem, an Genetic Algorithm (GA) was implemented to deal with larger cases. Several GAs crossovers and methodologies are compared for obtaining the best solution. Results show that best GA solution obtained, in average, communication costs with 4% of penalty when compared with best solution. In addition, the algorithm presents low execution times.

Mapeamento e posicionamento de módulos processantes em sistemas dinamicamente reconfiguráveis baseados em redes intrachip.