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This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO