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This paper reviews the options of using Atomic Layer Deposition (ALD) in passive and heterogeneous integration. The miniaturization intended by both integration schemes aim at Si-based integration for the former and at die stacking in a compact System-in-Package for the latter. In future Si-based integrated passives a next miniaturization step in trench capacitors requires the use of multiple ‘classical’ MOS layer stacks and the use of so-called high-k dielectrics (based on HfO2, etc.) and novel conductive layers like TiN, etc. to compose MIS and MIM stacks in ‘trench’ and ‘pore’ capacitors with capacitance densities exceeding 200 nF/mm 2 . One of the major challenges in realizing ultrahigh-density trench capacitors is to find an attractive pore lining and filling fabrication technology at reasonable cost and reaction rate as well as low temperature (for back-end processing freedom). As the deposition for the dielectric and conductive layers should be highly uniform, step-conformal and lowtemperature (≤ 400 °C), ALD is an enabling technology here, by virtue of the self-limiting mechanism of this layer-by-layer deposition technique. This article discusses first a few examples of LPCVD deposition of conventional MOS layers with ONO-dielectrics and in situ doped polycrystalline silicon, both as single layers and multilayer stacks. In addition, a few options for ALD deposition of thin dielectric and conductive layers (e.g. HfO2- and TiN-based) will be discussed. The silicon substrates that were used contained high aspect ratio (≥ 20) features with cross-section and spacing of the order of 1 µm.

ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs