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With increasing clock frequencies and silicon integration,power aware computing has become a critical concernin the design of embedded processors and systems-on-chip.One of the more effective and widely used methods for power-awarecomputing is dynamic voltage scaling (DVS). In orderto obtain the maximum power savings from DVS, it is essentialto scale the supply voltage as low as possible while ensuringcorrect operation of the processor. The critical voltage ischosen such that under a worst-case scenario of process andenvironmental variations, the processor always operates correctly.However, this approach leads to a very conservativesupply voltage since such a worst-case combination of differentvariabilities will be very rare. In this paper, we propose anew approach to DVS, called Razor, based on dynamic detectionand correction of circuit timing errors. The key idea ofRazor is to tune the supply voltage by monitoring the errorrate during circuit operation, thereby eliminating the need forvoltage margins and exploiting the data dependence of circuitdelay. A Razor flip-flop is introduced that double-samplespipeline stage values, once with a fast clock and again with atime-borrowing delayed clock. A metastability-tolerant comparatorthen validates latch values sampled with the fastclock. In the event of a timing error, a modified pipeline mispeculationrecovery mechanism restores correct programstate. A prototype Razor pipeline was designed in 0.18 µmtechnology and was analyzed. Razor energy overheads duringnormal operation are limited to 3.1%. Analyses of a full-custommultiplier and a SPICE-level Kogge-Stone addermodel reveal that substantial energy savings are possible forthese devices (up to 64.2%) with little impact on performancedue to error recovery (less than 3%).

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation