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A virtual instruction set architecture (V-ISA) implementedvia a processor-specific software translation layercan provide great flexibility to processor designers. Recentexamples such as Crusoe and DAISY, however, haveused existing hardware instruction sets as virtual ISAs,which complicates translation and optimization. In fact,there has been little research on specific designs for a virtualISA for processors. This paper proposes a novel virtualISA (LLVA) and a translation strategy for implementingit on arbitrary hardware. The instruction set is typed,uses an infinite virtual register set in Static Single Assignmentform, and provides explicit control-flow and dataflowinformation, and yet uses low-level operations closelymatched to traditional hardware. It includes novel mechanismsto allow more flexible optimization of native code,including a flexible exception model and minor constraintson self-modifying code. We propose a translationstrategy that enables offline translation and transparent offlinecaching of native code and profile information, whileremaining completely OS-independent. It also supports optimizationsdirectly on the representation at install-time,runtime, and offline between executions. We show experimentallythat despite its rich information content,virtual object code is comparable in size to native machinecode, virtual instructions expand to only 2-4 ordinaryhardware instructions on average, and simple translationcosts under 1% of total execution time except for veryshort runs.

LLVA: A Low-level Virtual Instruction Set Architecture