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The needs for Digital Logic Simulation to analyze design timing problems, such as spike and hazards, has been shown previously (1). In this paper, methods for detecting timing problems are investigated and analyzed. A technique is developed to perform spike and hazard analysis in a less pessimistic approach than has been used previously. It was implemented as an extension of the TEGAS2 simulation system (2) and is capable of associating different turn-on and turn-off propagation delays with an element.

Implemented techniques for handling spikes in an assignable delay simulator